Test Track at DATE 2007 - Call for Papers

CALL FOR PAPERS

Scope -- Test Topic Areas -- Author Information -- Information

Scope

The Design, Automation and Test in Europe conference and exhibition is the main European event bringing together design automation researchers, users and vendors, as well as specialists in the design, test, and manufacturing of electronic systems and circuits. One of the tracks of DATE is devoted to Methods, Tools and Innovative Experiences in Testing Electronic Circuits and Systems. At DATE 2007, we aim at the increase in the test area, and would really like to invite you to submit your contributions to the test track.

This five-day event consists of a conference with plenary keynotes, regular papers, interactive presentations, panels and hot-topic sessions, tutorials, master courses and workshops, as well as a Designers’ Forum. DATE is also Europe’s leading commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services. Both the conference and the exhibition, together with the many user group meetings, fringe meetings, university booth and social events offer a wide variety of opportunities to meet and exchange information.

Test Topic Areas

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The test track is organised in six topics. These topics together with their chairs and area descriptions are given as follows.

T1 System and Industrial Test
Chairs: Rainer Dorsch, IBM Deutschland Entwicklung, DE; Erik Larsson, Linkoping U, S

Testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, board, system; Network-on-Chip test; system-level debug and validation; hardware/software system test; processor-based test; infrastructure IP; industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies

T2 Design for Test and BIST
Chairs: Sybille Hellebrand, Paderborn U, DE; Alfredo Benso, Politecnico di Torino, IT

Design for test, debug and manufacturability; built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures.

T3 Test Generation, Simulation and Diagnosis
Chairs: Matteo Sonza Reorda, Politecnico di Torino, IT; Bernd Becker, Freiburg U, DE

Test pattern generation; high-level TPG; delay TPG; fault simulation; test generation for validation, debug and diagnosis; low-power TPG; TPG for memories and FPGAs.

T4 On-Line Testing, Fault Tolerance, and Reliability
Chairs: Cecilia Metra, Bologna U, IT; Fabrizio Lombardi, Northeastern U, US

Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; robust design; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; high reliability systems; reliability and dependability evaluation; safety; security; availability; reliability; hardware/software recovery; self-repair; fault tolerance; on-line testing and fault tolerance for industrial applications

T5 Testing of Analog, Mixed-Signal, RF and Heterogeous Circuits and Systems
Chairs: Abhijit Chatterjee, Georgia Inst. of Tech., US; Salvador Mir, TIMA, France

Failure modeling techniques for heterogeneous (analog/mixed-signal/RF/ MEMs/optics) circuits and systems; Fault simulation and test generation algorithms and coverage metrics; Low cost test techniques for high-performance RF and multi-GHz electronics and effective defect screening techniques; Testing of embedded MEMs/bio-MEMs/RF/ optics modules; Design-for-testability and built-in self-test (BIST) techniques for analog and mixed signal circuits; Test-diagnosis-repair of analog and mixed signal circuits; Industrial case studies

T6 Statistical, Physical, Defect-Based Testing and Test of Regular Structures
Chairs: Rob Aitken, ARM, US; Antonio Rubio, UPC, Spain

Includes techniques, circuits, and methodologies for test and detection of defects including non-visual, physical level, and parameter variation considerations, defect modelling, defect diagnosis, failure analysis, yield analysis, fault modelling, IDDx testing, Very Low Voltage testing, multiparameter testing, temperature testing, DFM and DFY, signal integrity and test methods analysis, as well as test techniques for regular structures such as RAM, FPGA, regular fabrics, EEPROM, and flash memory

Author Information

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All manuscripts must be submitted for review electronically, following the instructions on the conference Web page:

www.date-conference.com

The accepted file formats are PDF and Postscript. Manuscripts received in hard-copy form will not be processed.

Papers can be submitted for either standard oral presentation or for interactive presentation. Standard oral presentations require novel and complete research work supported by experimental results, and are held in front of a full audience. Besides these, DATE will again include interactive presentations of novel ideas that may require additional research or lack experimental data. Presentations are given on a laptop in a face-to-face discussion area.

Submissions should not exceed 6 pages in length for oral-presentation and 2 pages in length for interactive-presentation papers, and should be formatted as close as possible to the final format: A4 or letter sheets, double column, single spaced, Times or equivalent font of minimum 10pt (templates are available on the DATE Web site for your convenience). To permit blind review, submissions should not include the author names. Any submission not in line with the above rules will be discarded.

All papers will be evaluated with regard to their suitability for the conference, originality and technical soundness. The Programme Committee reserves the right to accept interesting contributions that do not meet the criteria for standard oral presentations, as interactive presentations.

Information

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Patrick Girard
DATE Test Track co-Chair
LIRMM
CNRS/University of Montpellier
34392 Montpellier, France
e-mail: girard@lirmm.fr

Jaume Segura
DATE Test Track co-Chair
Universitat de les Illes Balears
07122 Palma, Spain
e-mail: jaume.segura@uib.es

Jan Madsen
DATE Program Chair
Dept of Informatics and Mathematical Modelling
Technical University of Denmark,
DK-2800 Kgs. Lyngby, Denmark
e-mail: jan@imm.dtu.dk

For more information, visit us on the web at: http://www.date-conference.com/

The Design, Automation and Test in Europe Conference and Exhibition (DATE 2007) is sponsored by the European Design and Automation Association, the EDA Consortium, the IEEE Computer Society (TTTC), (CEDA), ECSI, RAS and ACM SIGDA.